--
-- DE2 (Cyclone-II) Entity for Interactive Project Game
-- Authors:
--      Abdulhamid Ghandour
--      Thomas John
--      Jaime Peretzman
--      Bharadwaj Vellore
--
-- Desc:
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity de2_vga_raster is
  
  port (
    reset      : in std_logic;
    clk	       : in std_logic; 
    read       : in  std_logic;
    write      : in  std_logic;
    chipselect : in  std_logic;
    address    : in  unsigned(4 downto 0);
    readdata   : out unsigned(15 downto 0);
    writedata  : in  unsigned(15 downto 0);
	
    VGA_CLK,                         -- Clock
    VGA_HS,                          -- H_SYNC
    VGA_VS,                          -- V_SYNC
    VGA_BLANK,                       -- BLANK
    VGA_SYNC : out std_logic;        -- SYNC
    VGA_R,                           -- Red[9:0]
    VGA_G,                           -- Green[9:0]
    VGA_B : out unsigned(9 downto 0) -- Blue[9:0]
    );

end de2_vga_raster;

architecture rtl of de2_vga_raster is
  
  -- Video parameters
  
  constant HTOTAL       : integer := 800;
  constant HSYNC        : integer := 96;
  constant HBACK_PORCH  : integer := 48;
  constant HACTIVE      : integer := 640;
  constant HFRONT_PORCH : integer := 16;
  
  constant VTOTAL       : integer := 525;
  constant VSYNC        : integer := 2;
  constant VBACK_PORCH  : integer := 33;
  constant VACTIVE      : integer := 480;
  constant VFRONT_PORCH : integer := 10;
  
  constant ball_dia : integer := 29;
  constant cross_dia : integer := 16;
  constant border : integer := 15;
  signal border_1,border_2,border_3,border_4 : unsigned (9 downto 0):="0000000000";
  signal C_H_start_1 : unsigned(9 downto 0) := "0000000000";
  signal C_V_Start_1 : unsigned(9 downto 0) := "0000000000";
  signal C_color_1   : unsigned(2 downto 0) := "000";
  signal C_H_start_2 : unsigned(9 downto 0) := "0000000000";
  signal C_V_Start_2 : unsigned(9 downto 0) := "0000000000";
  signal C_color_2   : unsigned(2 downto 0) := "000";
  signal C_H_start_3 : unsigned(9 downto 0) := "0000000000";
  signal C_V_Start_3 : unsigned(9 downto 0) := "0000000000";
  signal C_color_3   : unsigned(2 downto 0) := "000";
  signal C_H_start_4 : unsigned(9 downto 0) := "0000000000";
  signal C_V_Start_4 : unsigned(9 downto 0) := "0000000000";
  signal C_color_4   : unsigned(2 downto 0) := "000";
  signal C_H_start_5 : unsigned(9 downto 0) := "0000000000";
  signal C_V_Start_5 : unsigned(9 downto 0) := "0000000000";
  signal C_color_5   : unsigned(2 downto 0) := "000";
  signal C_H_start_6 : unsigned(9 downto 0) := "0000000000";
  signal C_V_Start_6 : unsigned(9 downto 0) := "0000000000";
  signal C_color_6   : unsigned(2 downto 0) := "000";
  signal C_H_start_7 : unsigned(9 downto 0) := "0000000000";
  signal C_V_Start_7 : unsigned(9 downto 0) := "0000000000";
  signal C_color_7   : unsigned(2 downto 0) := "000";


  signal  stick_H_1 : unsigned(9 downto 0) := "0000000000";
  signal  stick_V_1 : unsigned(9 downto 0) := "0000000000";
  signal  stick_H_2 : unsigned(9 downto 0) := "0000000000";
  signal  stick_V_2 : unsigned(9 downto 0) := "0000000000";
  signal  cross_H : unsigned(9 downto 0) := "0000000000";
  signal  cross_V : unsigned(9 downto 0) := "0000000000";

  signal temp_C_H_start_1 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_V_Start_1 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_color_1   : unsigned(2 downto 0) := "000";
  signal temp_C_H_start_2 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_V_Start_2 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_color_2   : unsigned(2 downto 0) := "000";
  signal temp_C_H_start_3 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_V_Start_3 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_color_3   : unsigned(2 downto 0) := "000";
  signal temp_C_H_start_4 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_V_Start_4 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_color_4   : unsigned(2 downto 0) := "000";
  signal temp_C_H_start_5 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_V_Start_5 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_color_5   : unsigned(2 downto 0) := "000";
  signal temp_C_H_start_6 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_V_Start_6 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_color_6   : unsigned(2 downto 0) := "000";
  signal temp_C_H_start_7 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_V_Start_7 : unsigned(9 downto 0) := "0000000000";
  signal temp_C_color_7   : unsigned(2 downto 0) := "000";
  signal temp_stick_H_1 : unsigned(9 downto 0) := "0000000000";
  signal temp_stick_V_1 : unsigned(9 downto 0) := "0000000000";
  signal temp_stick_H_2 : unsigned(9 downto 0) := "0000000000";
  signal temp_stick_V_2 : unsigned(9 downto 0) := "0000000000";
  signal temp_cross_H : unsigned(9 downto 0) := "0000000000";
  signal temp_cross_V : unsigned(9 downto 0) := "0000000000";
  
  signal Socket_H_start_11 : unsigned(9 downto 0) := "0000000000"; --0
  signal Socket_V_Start_11 : unsigned(9 downto 0) := "0000000000"; --0

  signal Socket_H_start_12 : unsigned(9 downto 0) := "0100110001"; --305
  signal Socket_V_Start_12 : unsigned(9 downto 0) := "0000000000"; --0

  signal Socket_H_start_13 : unsigned(9 downto 0) := "1001100010"; --610
  signal Socket_V_Start_13 : unsigned(9 downto 0) := "0000000000"; --0

  signal Socket_H_start_14 : unsigned(9 downto 0) := "0000000000"; --0
  signal Socket_V_Start_14 : unsigned(9 downto 0) := "0111000010"; --450

  signal Socket_H_start_15 : unsigned(9 downto 0) := "0100110001"; --305
  signal Socket_V_Start_15 : unsigned(9 downto 0) := "0111000010"; --450

  signal Socket_H_start_16 : unsigned(9 downto 0) := "1001100010"; --610
  signal Socket_V_Start_16 : unsigned(9 downto 0) := "0111000010"; --450

  signal received_check   : unsigned(20 downto 0) := "000000000000000000000";
  signal received_cal: unsigned(4 downto 0) := "00000";
  signal calibration: std_logic := '0';
  signal temp_border: std_logic :='0';
  signal margin : unsigned (4 downto 0):= "11111";

  -- Signals for the video controller
  signal Hcount : unsigned(9 downto 0);  -- Horizontal position (0-800)
  signal Vcount : unsigned(9 downto 0);  -- Vertical position (0-524) 
  signal EndOfLine, EndOfField : std_logic;
  signal clk25 : std_logic := '0';
  signal vga_hblank, vga_hsync,
    vga_vblank, vga_vsync : std_logic;  -- Sync. signals

  signal rectangle_00,rectangle_1, rectangle_2,rectangle_3,rectangle_4,rectangle_5,rectangle_6,rectangle_7 ,rectangle_11, rectangle_12,rectangle_13,rectangle_14,rectangle_15,rectangle_16,stick_h, stick_v, stick: std_logic;  -- rectangle area

  type color_mat is array (0 to 6) of unsigned (29 downto 0);
  constant color_RGB:color_mat :=   ("111111111111111111111111111111",
									"111111111111111111110000000000",
									"000000000011111111111111111111",
									"000000000011111111110000000000",
									"001111111111111111110011010101",
									"000100100011111111110011110011",
									"100000000011111111111000000000");

 type cross_matrix is array (0 to 15) of unsigned (0 to 15);
  constant cross_boundary:cross_matrix := ( "1111111111110000",
											"1100000000000000",
											"1010000000000000",
											"1001000000000000",
											"1000100000000000",
											"1000010000000000",
											"1000001000000000",
											"1000000100000000",
											"1000000010000000",
											"1000000001000000",
											"1000000000100000",
											"1000000000010000",
											"0000000000001000",
											"0000000000000100",
											"0000000000000010",
											"0000000000000001");
											
  type c_matrix is array (0 to 28) of unsigned (0 to 28);
  constant C_boundary:c_matrix :=      	("00000000001111111000000000000",
										"00000000011111111111000000000",
										"00000001111111111111110000000",
										"00000011111111111111111000000",
										"00000111111111111111111100000",
										"00001111111111111111111110000",
										"00011111111111111111111111000",
										"00111111111111111111111111100",
										"00111111111111111111111111100",
										"01111111111111111111111111110",
										"01111111111111111111111111110",
										"11111111111111111111111111111",
										"11111111111111111111111111111",
										"11111111111111111111111111111",
										"11111111111111111111111111111",
										"11111111111111111111111111111",
										"11111111111111111111111111111",
										"11111111111111111111111111111",
										"01111111111111111111111111110",
										"01111111111111111111111111110",
										"00111111111111111111111111100",
										"00111111111111111111111111100",
										"00011111111111111111111111000",
										"00001111111111111111111110000",
										"00000111111111111111111100000",
										"00000011111111111111111000000",
										"00000001111111111111110000000",
										"00000000011111111111000000000",
										"00000000000111111100000000000");

begin  

  process (clk)
  begin
    if rising_edge(clk) then
      clk25 <= not clk25;
    end if;
  end process;

  -- Horizontal and vertical counters

    soft_input : process (clk)
    variable temp_mid : unsigned(9 downto 0);
    begin
  	if rising_edge(clk) then
		if reset = '1' then
			temp_C_H_start_1 <= (others => '0');
			temp_C_V_Start_1 <= (others => '0');
			temp_C_color_1 	 <= (others => '0');
			C_H_start_1	 <= (others => '0');
			C_V_start_1 	 <= (others => '0');
			C_color_1 	 <= (others => '0');
			temp_C_H_start_2 <= (others => '0');
			temp_C_V_Start_2 <= (others => '0');
			temp_C_color_2   <= (others => '0');
			C_H_start_2	 <= (others => '0');
			C_V_start_2 	 <= (others => '0');
			C_color_2 	 <= (others => '0');
			temp_C_H_start_3 <= (others => '0');
			temp_C_V_Start_3 <= (others => '0');
			temp_C_color_3 	 <= (others => '0');
			C_H_start_3	 <= (others => '0');
			C_V_start_3 	 <= (others => '0');
			C_color_3 	 <= (others => '0');
			temp_C_H_start_4 <= (others => '0');
			temp_C_V_Start_4 <= (others => '0');
			temp_C_color_4 	 <= (others => '0');
			C_H_start_4	 <= (others => '0');
			C_V_start_4 	 <= (others => '0');
			C_color_4 	 <= (others => '0');
			temp_C_H_start_5 <= (others => '0');
			temp_C_V_Start_5 <= (others => '0');
			temp_C_color_5   <= (others => '0');
			C_H_start_5	 <= (others => '0');
			C_V_start_5 	 <= (others => '0');
			C_color_5 	 <= (others => '0');
			temp_C_H_start_6 <= (others => '0');
			temp_C_V_Start_6 <= (others => '0');
			temp_C_color_6 	 <= (others => '0');
			C_H_start_6	 <= (others => '0');
			C_V_start_6 	 <= (others => '0');
			C_color_6 	 <= (others => '0');
			temp_C_H_start_7 <= (others => '0');
			temp_C_V_Start_7 <= (others => '0');
			temp_C_color_7 	 <= (others => '0');
			C_H_start_7	 <= (others => '0');
			C_V_start_7 	 <= (others => '0');
			C_color_7 	 <= (others => '0');
            received_check   <= (others => '0');
			received_cal <= (others => '0');
		else
           if chipselect = '1' then
  			if write = '1' then
  				if address =  "00000" then
  					temp_C_H_start_1 <= writedata(9 downto 0);
					received_check(0) <= '1';
  				elsif address = "00001" then
   			        	temp_C_V_Start_1 <= writedata(9 downto 0);
					received_check(1) <= '1';
 				elsif address =  "00010" then
  					temp_C_color_1 <= writedata(2 downto 0);
					received_check(2) <= '1';

 				elsif address =  "00011" then
  					temp_C_H_start_2 <= writedata(9 downto 0);
					received_check(3) <= '1';			
  				elsif address = "00100" then
   			        	temp_C_V_Start_2 <= writedata(9 downto 0);
					received_check(4) <= '1';
 				elsif address =  "00101" then
  					temp_C_color_2 <= writedata(2 downto 0);
					received_check(5) <= '1';


 				elsif address =  "00110" then
  					temp_C_H_start_3 <= writedata(9 downto 0);
					received_check(6) <= '1';
				elsif address = "00111" then
   			        	temp_C_V_Start_3 <= writedata(9 downto 0);
					received_check(7) <= '1';
 				elsif address =  "01000" then
  					temp_C_color_3 <= writedata(2 downto 0);
					received_check(8) <= '1';


 				elsif address =  "01001" then
  					temp_C_H_start_4 <= writedata(9 downto 0);
					received_check(9) <= '1';
  				elsif address = "01010" then
   			        	temp_C_V_Start_4 <= writedata(9 downto 0);
					received_check(10) <= '1';
 				elsif address =  "01011" then
  					temp_C_color_4 <= writedata(2 downto 0);
					received_check(11) <= '1';

 				elsif address =  "10110" then
  					temp_C_H_start_5 <= writedata(9 downto 0);
					received_check(12) <= '1';
  				elsif address = "10111" then
   			        	temp_C_V_Start_5 <= writedata(9 downto 0);
					received_check(13) <= '1';
 				elsif address =  "11000" then
  					temp_C_color_5 <= writedata(2 downto 0);
					received_check(14) <= '1';

 				elsif address =  "11001" then
  					temp_C_H_start_6 <= writedata(9 downto 0);
					received_check(15) <= '1';
  				elsif address = "11010" then
   			        	temp_C_V_Start_6 <= writedata(9 downto 0);
					received_check(16) <= '1';
 				elsif address =  "11011" then
  					temp_C_color_6 <= writedata(2 downto 0);
					received_check(17) <= '1'; 
					
 				elsif address =  "11100" then
  					temp_C_H_start_7 <= writedata(9 downto 0);
					received_check(18) <= '1';
  				elsif address = "11101" then
   			        	temp_C_V_Start_7 <= writedata(9 downto 0);
					received_check(19) <= '1';
 				elsif address =  "11110" then
  					temp_C_color_7 <= writedata(2 downto 0);
					received_check(20) <= '1';  	
					 				
				
				elsif address =  "01101" then
  					temp_cross_H<= writedata(9 downto 0);
					
  				elsif address = "01110" then
   			        temp_cross_V <= writedata(9 downto 0);
					

				elsif address =  "10000" then
  					temp_stick_H_1 <= writedata(9 downto 0);
					received_cal(0) <= '1';
  				elsif address = "10001" then
   			        temp_stick_V_1 <= writedata(9 downto 0);
					received_cal(1) <= '1';
				elsif address =  "10010" then
  					temp_stick_H_2 <= writedata(9 downto 0);
					received_cal(2) <= '1';
  				elsif address = "10011" then
   			        temp_stick_V_2 <= writedata(9 downto 0);
					received_cal(3) <= '1';
				elsif address = "10101" then --21
					--temp_border <= '0';
   			        temp_border <= writedata(0);
					received_cal(4) <= '1';
					
 				
  				end if;  -- end of if address
                          
  			end if;         -- end of if write
                        if read = '1' and address = "01100" then
							if received_check ="000000000000000000000" then
                               readdata(0) <= '0';
                            else                         
                                readdata(0) <='1';
                            end if;
                        end if;         --end of read
						if read = '1' and address = "10100" then
							if received_cal ="00000" then
                               readdata(0) <= '0';
                            else                         
                                readdata(0) <='1';
                            end if;
                        end if;         --end of read
		   end if; --ship select
			if EndOfLine = '1' and EndOfField = '1' then 
			  if received_check = "111111111111111111111" then
				C_H_start_1 <= temp_C_H_start_1;
				C_V_Start_1 <= temp_C_V_Start_1;
				C_color_1   <= temp_C_color_1;
				C_H_start_2 <= temp_C_H_start_2;
				C_V_Start_2 <= temp_C_V_Start_2;
				C_color_2   <= temp_C_color_2;
				C_H_start_3 <= temp_C_H_start_3;
				C_V_Start_3 <= temp_C_V_Start_3;
				C_color_3   <= temp_C_color_3;
				C_H_start_4 <= temp_C_H_start_4;
				C_V_Start_4 <= temp_C_V_Start_4;
				C_color_4   <= temp_C_color_4;
				C_H_start_5 <= temp_C_H_start_5;
				C_V_Start_5 <= temp_C_V_Start_5;
				C_color_5   <= temp_C_color_5;
				C_H_start_6 <= temp_C_H_start_6;
				C_V_Start_6 <= temp_C_V_Start_6;
				C_color_6   <= temp_C_color_6;
				C_H_start_7 <= temp_C_H_start_7;
				C_V_Start_7 <= temp_C_V_Start_7;
				C_color_7   <= temp_C_color_7;
				cross_H <=temp_cross_H;
				cross_V <=temp_cross_V;
				calibration <= '0';
				received_check <= (others => '0');
			   elsif received_cal="11111" and temp_border ='0' then
			    stick_H_1 <= temp_stick_H_1;
			    stick_V_1 <= temp_stick_V_1;
			    stick_H_2 <= temp_stick_H_2;
			    stick_V_2 <= temp_stick_V_2;
				cross_H <=temp_cross_H;
				cross_V <=temp_cross_V;
				calibration<='1';
				received_cal <= (others=>'0');
				elsif received_cal="11111" and temp_border ='1' then
				border_1 <= temp_stick_H_1;
				border_2 <= temp_stick_V_1;
				border_3 <= temp_stick_H_2;
				border_4 <= temp_stick_V_2;
				temp_mid := (temp_stick_H_1+temp_stick_H_2-border-border);
				Socket_H_start_11 <= (temp_stick_H_1-border);
				Socket_H_start_14 <= (temp_stick_H_1-border);
			    Socket_V_start_11 <= (temp_stick_V_1-border);
				Socket_V_start_12 <= (temp_stick_V_1-border);
				Socket_V_start_13 <= (temp_stick_V_1-border);
				Socket_H_start_13 <= (temp_stick_H_2-border);
				Socket_H_start_16 <= (temp_stick_H_2-border);
				Socket_V_start_14 <= (temp_stick_V_2-border);
				Socket_V_start_15 <= (temp_stick_V_2-border);
				Socket_V_start_16 <= (temp_stick_V_2-border);
				Socket_H_start_12 <= ('0'&(temp_mid(9 downto 1)));
				Socket_H_start_15 <= ('0'&(temp_mid(9 downto 1)));
				cross_H <=temp_cross_H;
				cross_V <=temp_cross_V;
				calibration<='0';
				received_cal <= (others=>'0');		
				
			   end if;
			end  if;
			
		end if;
  	end if;
    end process soft_input;


  HCounter : process (clk25)
  begin
    if rising_edge(clk25) then      
      if reset = '1' then
        Hcount <= (others => '0');
      elsif EndOfLine = '1' then
        Hcount <= (others => '0');
      else
        Hcount <= Hcount + 1;
      end if;      
    end if;
  end process HCounter;

  EndOfLine <= '1' when Hcount = HTOTAL - 1 else '0';
  
  VCounter: process (clk25)
  begin
    if rising_edge(clk25) then      
      if reset = '1' then
        Vcount <= (others => '0');
      elsif EndOfLine = '1' then
        if EndOfField = '1' then
          Vcount <= (others => '0');
        else
          Vcount <= Vcount + 1;
        end if;
      end if;
    end if;
  end process VCounter;

  EndOfField <= '1' when Vcount = VTOTAL - 1 else '0';

  -- State machines to generate HSYNC, VSYNC, HBLANK, and VBLANK

  HSyncGen : process (clk25)
  begin
    if rising_edge(clk25) then     
      if reset = '1' or EndOfLine = '1' then
        vga_hsync <= '1';
      elsif Hcount = HSYNC - 1 then
        vga_hsync <= '0';
      end if;
    end if;
  end process HSyncGen;
  
  HBlankGen : process (clk25)
  begin
    if rising_edge(clk25) then
      if reset = '1' then
        vga_hblank <= '1';
      elsif Hcount = HSYNC + HBACK_PORCH then
        vga_hblank <= '0';
      elsif Hcount = HSYNC + HBACK_PORCH + HACTIVE then
        vga_hblank <= '1';
      end if;      
    end if;
  end process HBlankGen;

  VSyncGen : process (clk25)
  begin
    if rising_edge(clk25) then
      if reset = '1' then
        vga_vsync <= '1';
      elsif EndOfLine ='1' then
        if EndOfField = '1' then
          vga_vsync <= '1';
        elsif Vcount = VSYNC - 1 then
          vga_vsync <= '0';
        end if;
      end if;      
    end if;
  end process VSyncGen;

  VBlankGen : process (clk25)
  begin
    if rising_edge(clk25) then    
      if reset = '1' then
        vga_vblank <= '1';
      elsif EndOfLine = '1' then
        if Vcount = VSYNC + VBACK_PORCH - 1 then
          vga_vblank <= '0';
        elsif Vcount = VSYNC + VBACK_PORCH + VACTIVE - 1 then
          vga_vblank <= '1';
        end if;
      end if;
    end if;
  end process VBlankGen;






----------------------------------------------------------------------------------------------------------







  -- BALL generator 1

  RectangleHGen_1 : process (clk25)
  variable H_boundary : unsigned(0 to 28);
  variable h_index_1 : unsigned(9 downto 0); 
  variable v_index_1 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_1 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + C_H_start_1 - 1 and Vcount > VSYNC + VBACK_PORCH +  C_V_Start_1 - 1 then
        if Hcount < HSYNC + HBACK_PORCH + C_H_start_1 + ball_dia and Vcount < VSYNC + VBACK_PORCH + C_V_Start_1 + ball_dia then
                h_index_1 := Hcount - HSYNC - HBACK_PORCH - C_H_start_1 ;
		v_index_1 := Vcount - VSYNC - VBACK_PORCH - C_V_Start_1 ;
		H_boundary := (others => '0');
		H_boundary := C_boundary(TO_INTEGER(v_index_1));
			if H_boundary(TO_INTEGER(h_index_1)) = '1' then
				rectangle_1 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_1)) = '0' then
				rectangle_1 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + C_H_start_1 + ball_dia then
		rectangle_1 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + C_H_start_1 + ball_dia then
	  rectangle_1 <= '0';
      end if;     
    end if;
  end process RectangleHGen_1;


  -- BALL generator 2

  RectangleHGen_2 : process (clk25)
  variable H_boundary : unsigned(0 to 28);
  variable h_index_2 : unsigned(9 downto 0); 
  variable v_index_2 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_2 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + C_H_start_2 - 1 and Vcount > VSYNC + VBACK_PORCH +  C_V_Start_2 - 1 then
        if Hcount < HSYNC + HBACK_PORCH + C_H_start_2 + ball_dia and Vcount < VSYNC + VBACK_PORCH + C_V_Start_2 + ball_dia then
                h_index_2 := Hcount - HSYNC - HBACK_PORCH - C_H_start_2 ;
		v_index_2 := Vcount - VSYNC - VBACK_PORCH - C_V_Start_2 ;
		H_boundary := (others => '0');
		H_boundary := C_boundary(TO_INTEGER(v_index_2));
			if H_boundary(TO_INTEGER(h_index_2)) = '1' then
				rectangle_2 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_2)) = '0' then
				rectangle_2 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + C_H_start_2 + ball_dia then
		rectangle_2 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + C_H_start_2 + ball_dia then
	  rectangle_2 <= '0';
      end if;     
    end if;
  end process RectangleHGen_2;


  -- BALL generator 3

  RectangleHGen_3 : process (clk25)
  variable H_boundary : unsigned(0 to 28);
  variable h_index_3 : unsigned(9 downto 0); 
  variable v_index_3 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_3 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + C_H_start_3 - 1 and Vcount > VSYNC + VBACK_PORCH +  C_V_Start_3 - 1 then
        if Hcount < HSYNC + HBACK_PORCH + C_H_start_3 + ball_dia and Vcount < VSYNC + VBACK_PORCH + C_V_Start_3 + ball_dia then
                h_index_3 := Hcount - HSYNC - HBACK_PORCH - C_H_start_3 ;
		v_index_3 := Vcount - VSYNC - VBACK_PORCH - C_V_Start_3 ;
		H_boundary := (others => '0');
		H_boundary := C_boundary(TO_INTEGER(v_index_3));
			if H_boundary(TO_INTEGER(h_index_3)) = '1' then
				rectangle_3 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_3)) = '0' then
				rectangle_3 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + C_H_start_3 + ball_dia then
		rectangle_3 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + C_H_start_3 + ball_dia then
	  rectangle_3 <= '0';
      end if;     
    end if;
  end process RectangleHGen_3;


  -- BALL generator 4

  RectangleHGen_4 : process (clk25)
  variable H_boundary : unsigned(0 to 28);
  variable h_index_4 : unsigned(9 downto 0); 
  variable v_index_4 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_4 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + C_H_start_4 - 1 and Vcount > VSYNC + VBACK_PORCH +  C_V_Start_4 - 1 then
        if Hcount < HSYNC + HBACK_PORCH + C_H_start_4 + ball_dia and Vcount < VSYNC + VBACK_PORCH + C_V_Start_4 + ball_dia then
                h_index_4 := Hcount - HSYNC - HBACK_PORCH - C_H_start_4 ;
		v_index_4 := Vcount - VSYNC - VBACK_PORCH - C_V_Start_4 ;
		H_boundary := (others => '0');
		H_boundary := C_boundary(TO_INTEGER(v_index_4));
			if H_boundary(TO_INTEGER(h_index_4)) = '1' then
				rectangle_4 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_4)) = '0' then
				rectangle_4 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + C_H_start_4 + ball_dia then
		rectangle_4 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + C_H_start_4 + ball_dia then
	  rectangle_4 <= '0';
      end if;     
    end if;
  end process RectangleHGen_4;

  -- BALL generator 5

  RectangleHGen_5 : process (clk25)
  variable H_boundary : unsigned(0 to 28);
  variable h_index_5 : unsigned(9 downto 0); 
  variable v_index_5 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_5 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + C_H_start_5 - 1 and Vcount > VSYNC + VBACK_PORCH +  C_V_Start_5 - 1 then
        if Hcount < HSYNC + HBACK_PORCH + C_H_start_5 + ball_dia and Vcount < VSYNC + VBACK_PORCH + C_V_Start_5 + ball_dia then
                h_index_5 := Hcount - HSYNC - HBACK_PORCH - C_H_start_5 ;
		v_index_5 := Vcount - VSYNC - VBACK_PORCH - C_V_Start_5 ;
		H_boundary := (others => '0');
		H_boundary := C_boundary(TO_INTEGER(v_index_5));
			if H_boundary(TO_INTEGER(h_index_5)) = '1' then
				rectangle_5 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_5)) = '0' then
				rectangle_5 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + C_H_start_5 + ball_dia then
		rectangle_5 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + C_H_start_5 + ball_dia then
	  rectangle_5 <= '0';
      end if;     
    end if;
  end process RectangleHGen_5;

  -- BALL generator 6

  RectangleHGen_6 : process (clk25)
  variable H_boundary : unsigned(0 to 28);
  variable h_index_6 : unsigned(9 downto 0); 
  variable v_index_6 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_6 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + C_H_start_6 - 1 and Vcount > VSYNC + VBACK_PORCH +  C_V_Start_6 - 1 then
        if Hcount < HSYNC + HBACK_PORCH + C_H_start_6 + ball_dia and Vcount < VSYNC + VBACK_PORCH + C_V_Start_6 + ball_dia then
                h_index_6 := Hcount - HSYNC - HBACK_PORCH - C_H_start_6 ;
		v_index_6 := Vcount - VSYNC - VBACK_PORCH - C_V_Start_6 ;
		H_boundary := (others => '0');
		H_boundary := C_boundary(TO_INTEGER(v_index_6));
			if H_boundary(TO_INTEGER(h_index_6)) = '1' then
				rectangle_6 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_6)) = '0' then
				rectangle_6 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + C_H_start_6 + ball_dia then
		rectangle_6 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + C_H_start_6 + ball_dia then
	  rectangle_6 <= '0';
      end if;     
    end if;
  end process RectangleHGen_6;


  -- BALL generator 7

  RectangleHGen_7 : process (clk25)
  variable H_boundary : unsigned(0 to 28);
  variable h_index_7 : unsigned(9 downto 0); 
  variable v_index_7 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_7 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + C_H_start_7 - 1 and Vcount > VSYNC + VBACK_PORCH +  C_V_Start_7 - 1 then
        if Hcount < HSYNC + HBACK_PORCH + C_H_start_7 + ball_dia and Vcount < VSYNC + VBACK_PORCH + C_V_Start_7 + ball_dia then
                h_index_7 := Hcount - HSYNC - HBACK_PORCH - C_H_start_7 ;
		v_index_7 := Vcount - VSYNC - VBACK_PORCH - C_V_Start_7 ;
		H_boundary := (others => '0');
		H_boundary := C_boundary(TO_INTEGER(v_index_7));
			if H_boundary(TO_INTEGER(h_index_7)) = '1' then
				rectangle_7 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_7)) = '0' then
				rectangle_7 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + C_H_start_7 + ball_dia then
		rectangle_7 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + C_H_start_7 + ball_dia then
	  rectangle_7 <= '0';
      end if;     
    end if;
  end process RectangleHGen_7;


 -- Socket  generator 1

  RectangleHGen_11: process (clk25)
  variable H_boundary : unsigned(0 to 28);
  variable h_index_11 : unsigned(9 downto 0); 
  variable v_index_11 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_11 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + Socket_H_start_11 - 1 and Vcount > VSYNC + VBACK_PORCH +  Socket_V_Start_11 - 1 then
        if Hcount < HSYNC + HBACK_PORCH + Socket_H_start_11 + ball_dia and Vcount < VSYNC + VBACK_PORCH + Socket_V_Start_11 + ball_dia then
                h_index_11 := Hcount - HSYNC - HBACK_PORCH - Socket_H_start_11 ;
		v_index_11 := Vcount - VSYNC - VBACK_PORCH - Socket_V_Start_11 ;
		H_boundary := (others => '0');
		H_boundary := C_boundary(TO_INTEGER(v_index_11));
			if H_boundary(TO_INTEGER(h_index_11)) = '1' then
				rectangle_11 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_11)) = '0' then
				rectangle_11 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + Socket_H_start_11 + ball_dia then
		rectangle_11 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + Socket_H_start_11 + ball_dia then
	  rectangle_11 <= '0';
      end if;     
    end if;
  end process RectangleHGen_11;


 -- Socket  generator 2

  RectangleHGen_12: process (clk25)
  variable H_boundary : unsigned(0 to 28);
  variable h_index_12 : unsigned(9 downto 0); 
  variable v_index_12 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_12 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + Socket_H_start_12 - 1 and Vcount > VSYNC + VBACK_PORCH +  Socket_V_Start_12 - 1 then
        if Hcount < HSYNC + HBACK_PORCH + Socket_H_start_12 + ball_dia and Vcount < VSYNC + VBACK_PORCH + Socket_V_Start_12 + ball_dia then
                h_index_12 := Hcount - HSYNC - HBACK_PORCH - Socket_H_start_12 ;
		v_index_12 := Vcount - VSYNC - VBACK_PORCH - Socket_V_Start_12 ;
		H_boundary := (others => '0');
		H_boundary := C_boundary(TO_INTEGER(v_index_12));
			if H_boundary(TO_INTEGER(h_index_12)) = '1' then
				rectangle_12 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_12)) = '0' then
				rectangle_12 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + Socket_H_start_12 + ball_dia then
		rectangle_12 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + Socket_H_start_12 + ball_dia then
	  rectangle_12 <= '0';
      end if;     
    end if;
  end process RectangleHGen_12;

 -- Socket  generator 3

  RectangleHGen_13: process (clk25)
  variable H_boundary : unsigned(0 to 28);
  variable h_index_13 : unsigned(9 downto 0); 
  variable v_index_13 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_13 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + Socket_H_start_13 - 1 and Vcount > VSYNC + VBACK_PORCH +  Socket_V_Start_13 - 1 then
        if Hcount < HSYNC + HBACK_PORCH + Socket_H_start_13 + ball_dia and Vcount < VSYNC + VBACK_PORCH + Socket_V_Start_13 + ball_dia then
                h_index_13 := Hcount - HSYNC - HBACK_PORCH - Socket_H_start_13 ;
		v_index_13 := Vcount - VSYNC - VBACK_PORCH - Socket_V_Start_13 ;
		H_boundary := (others => '0');
		H_boundary := C_boundary(TO_INTEGER(v_index_13));
			if H_boundary(TO_INTEGER(h_index_13)) = '1' then
				rectangle_13 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_13)) = '0' then
				rectangle_13 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + Socket_H_start_13 + ball_dia then
		rectangle_13 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + Socket_H_start_13 + ball_dia then
	  rectangle_13 <= '0';
      end if;     
    end if;
  end process RectangleHGen_13;

 -- Socket  generator 4

  RectangleHGen_14: process (clk25)
  variable H_boundary : unsigned(0 to 28);
  variable h_index_14 : unsigned(9 downto 0); 
  variable v_index_14 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_14 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + Socket_H_start_14 - 1 and Vcount > VSYNC + VBACK_PORCH +  Socket_V_Start_14 - 1 then
        if Hcount < HSYNC + HBACK_PORCH + Socket_H_start_14 + ball_dia and Vcount < VSYNC + VBACK_PORCH + Socket_V_Start_14 + ball_dia then
                h_index_14 := Hcount - HSYNC - HBACK_PORCH - Socket_H_start_14 ;
		v_index_14 := Vcount - VSYNC - VBACK_PORCH - Socket_V_Start_14 ;
		H_boundary := (others => '0');
		H_boundary := C_boundary(TO_INTEGER(v_index_14));
			if H_boundary(TO_INTEGER(h_index_14)) = '1' then
				rectangle_14 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_14)) = '0' then
				rectangle_14 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + Socket_H_start_14 + ball_dia then
		rectangle_14 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + Socket_H_start_14 + ball_dia then
	  rectangle_14 <= '0';
      end if;     
    end if;
  end process RectangleHGen_14;

 -- Socket  generator 5

  RectangleHGen_15: process (clk25)
  variable H_boundary : unsigned(0 to 28);
  variable h_index_15 : unsigned(9 downto 0); 
  variable v_index_15 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_15 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + Socket_H_start_15 - 1 and Vcount > VSYNC + VBACK_PORCH +  Socket_V_Start_15 - 1 then
        if Hcount < HSYNC + HBACK_PORCH + Socket_H_start_15 + ball_dia and Vcount < VSYNC + VBACK_PORCH + Socket_V_Start_15 + ball_dia then
                h_index_15 := Hcount - HSYNC - HBACK_PORCH - Socket_H_start_15 ;
		v_index_15 := Vcount - VSYNC - VBACK_PORCH - Socket_V_Start_15 ;
		H_boundary := (others => '0');
		H_boundary := C_boundary(TO_INTEGER(v_index_15));
			if H_boundary(TO_INTEGER(h_index_15)) = '1' then
				rectangle_15 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_15)) = '0' then
				rectangle_15 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + Socket_H_start_15 + ball_dia then
		rectangle_15 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + Socket_H_start_15 + ball_dia then
	  rectangle_15 <= '0';
      end if;     
    end if;
  end process RectangleHGen_15;

 -- Socket  generator 6

  RectangleHGen_16: process (clk25)
  variable H_boundary : unsigned(0 to 28);
  variable h_index_16 : unsigned(9 downto 0); 
  variable v_index_16 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_16 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + Socket_H_start_16 - 1 and Vcount > VSYNC + VBACK_PORCH +  Socket_V_Start_16 - 1 then
        if Hcount < HSYNC + HBACK_PORCH + Socket_H_start_16 + ball_dia and Vcount < VSYNC + VBACK_PORCH + Socket_V_Start_16 + ball_dia then
                h_index_16 := Hcount - HSYNC - HBACK_PORCH - Socket_H_start_16 ;
		v_index_16 := Vcount - VSYNC - VBACK_PORCH - Socket_V_Start_16 ;
		H_boundary := (others => '0');
		H_boundary := C_boundary(TO_INTEGER(v_index_16));
			if H_boundary(TO_INTEGER(h_index_16)) = '1' then
				rectangle_16 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_16)) = '0' then
				rectangle_16 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + Socket_H_start_16 + ball_dia then
		rectangle_16 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + Socket_H_start_16 + ball_dia then
	  rectangle_16 <= '0';
      end if;     
    end if;
  end process RectangleHGen_16;



  -----stick for calibration
  
   RectangleHGen : process (clk25)
  begin
    if rising_edge(clk) then     
      if reset = '1' or Hcount = HSYNC + HBACK_PORCH + stick_H_1 then
        stick_h <= '1';
      elsif Hcount = HSYNC + HBACK_PORCH + stick_H_2 then
        stick_h <= '0';
      end if;      
    end if;
  end process RectangleHGen;

  RectangleVGen : process (clk25)
  begin
    if rising_edge(clk) then
      if reset = '1' then       
        stick_v <= '0';
      elsif EndOfLine = '1' then
        if Vcount = VSYNC + VBACK_PORCH - 1 + stick_V_1 then
          stick_v <= '1';
        elsif Vcount = VSYNC + VBACK_PORCH - 1 + stick_V_2 then
          stick_v <= '0';
        end if;
      end if;      
    end if;
  end process RectangleVGen;

  stick <= stick_h and stick_v;

  
  -----------crosshair-------
   RectangleHGen_00 : process (clk25)
  variable H_boundary : unsigned(0 to 15);
  variable h_index_00 : unsigned(9 downto 0); 
  variable v_index_00 : unsigned(9 downto 0);

  begin
    if rising_edge(clk25) then  
	if reset = '1' then   
	  rectangle_00 <= '0';
      elsif Hcount > HSYNC + HBACK_PORCH + cross_H - 1 and Vcount > VSYNC + VBACK_PORCH +  cross_V - 1 then
        if Hcount < HSYNC + HBACK_PORCH + cross_H + cross_dia and Vcount < VSYNC + VBACK_PORCH + cross_V + cross_dia then
        h_index_00 := Hcount - HSYNC - HBACK_PORCH - cross_H ;
		v_index_00 := Vcount - VSYNC - VBACK_PORCH - cross_V ;
		H_boundary := (others => '0');
		H_boundary := cross_boundary(TO_INTEGER(v_index_00));
			if H_boundary(TO_INTEGER(h_index_00)) = '1' then
				rectangle_00 <= '1';
			elsif H_boundary(TO_INTEGER(h_index_00)) = '0' then
				rectangle_00 <= '0';
			end if;
        elsif Hcount >= HSYNC + HBACK_PORCH + cross_H + cross_dia then
		rectangle_00 <= '0';
        end if; 
      elsif Hcount = HSYNC + HBACK_PORCH + cross_H + cross_dia then
	  rectangle_00 <= '0';
      end if;     
    end if;
  end process RectangleHGen_00;

----------------output
  VideoOut: process (clk25, reset)
		
  begin
    if reset = '1' then
      VGA_R <= "0000000000";
      VGA_G <= "0000000000";
      VGA_B <= "0000000000";
    elsif clk25'event and clk25 = '1' then
		   if calibration = '1' then
				if rectangle_00 = '1' then
				  VGA_R <= "1111111111";    
	    	      VGA_G <= "1111111111";
 		          VGA_B <= "1111111111";
		        elsif stick = '1' then
					VGA_R <= "0000000000";
					VGA_G <= "0000000000";
					VGA_B <= "0000000000";
			    elsif vga_hblank = '0' and vga_vblank ='0' then
			        VGA_R <= "0000000000";
			        VGA_G <= "1111111111";
			        VGA_B <= "0000000000";
			    else
			        VGA_R <= "0000000000";
			        VGA_G <= "0000000000";
			        VGA_B <= "0000000000";    
			    end if;
		   else
		
		
		   if rectangle_00 = '1' then
				  VGA_R <= "1111111111";    
	    	      VGA_G <= "1111111111";
 		          VGA_B <= "1111111111";		
		
          elsif ( Hcount >= HSYNC + HBACK_PORCH and Hcount < HSYNC + HBACK_PORCH + 641 and
            ((Vcount >= VSYNC + VBACK_PORCH and Vcount <VSYNC + VBACK_PORCH+ to_integer(border_2)+ 1 -to_integer(margin))or(Vcount > VSYNC + VBACK_PORCH+ to_integer(border_4)-1+to_integer(margin) and Vcount <VSYNC + VBACK_PORCH+480)))or
            ( Vcount >= VSYNC + VBACK_PORCH and Vcount < VSYNC + VBACK_PORCH + 480 and
           ((Hcount >= HSYNC + HBACK_PORCH and Hcount <HSYNC + HBACK_PORCH+ to_integer(border_1) + 1 -to_integer(margin))or(Hcount >= HSYNC + HBACK_PORCH+to_integer(border_3)-1+to_integer(margin) and Hcount <HSYNC + HBACK_PORCH+641)))then
 		          VGA_R <= "1111111111";    
	    	      VGA_G <= "1111111111";
 		          VGA_B <= "0000000000";		
           elsif ( Hcount >= HSYNC + HBACK_PORCH and Hcount < HSYNC + HBACK_PORCH + 641 and
            ((Vcount >= VSYNC + VBACK_PORCH+ to_integer(border_2)+ 1 -to_integer(margin) and Vcount <VSYNC + VBACK_PORCH+ to_integer(border_2)+ 1)or(Vcount > VSYNC + VBACK_PORCH+ to_integer(border_4)-1 and Vcount <=VSYNC + VBACK_PORCH+to_integer(border_4)-1+to_integer(margin))))or
            ( Vcount >= VSYNC + VBACK_PORCH and Vcount < VSYNC + VBACK_PORCH + 480 and
           ((Hcount >= HSYNC + HBACK_PORCH + to_integer(border_1) + 1 -to_integer(margin)and Hcount <HSYNC + HBACK_PORCH+ to_integer(border_1) + 1)or(Hcount > HSYNC + HBACK_PORCH+to_integer(border_3)-1 and Hcount <HSYNC + HBACK_PORCH+to_integer(border_3)-1+to_integer(margin))))then
 		          VGA_R <= "1111111111";    
	    	      VGA_G <= "1111111111";
 		          VGA_B <= "0000000000";

           elsif rectangle_1 = '1' and C_color_1 /="011"then
		     	  VGA_R <= color_RGB(TO_INTEGER(C_color_1))(29 downto 20);
			      VGA_G <= color_RGB(TO_INTEGER(C_color_1))(19 downto 10);
	              VGA_B <= color_RGB(TO_INTEGER(C_color_1))(9 downto 0);
	       elsif rectangle_2 = '1' and C_color_2 /="011"then
       		      VGA_R <= color_RGB(TO_INTEGER(C_color_2))(29 downto 20);
		     	  VGA_G <= color_RGB(TO_INTEGER(C_color_2))(19 downto 10);
			      VGA_B <= color_RGB(TO_INTEGER(C_color_2))(9 downto 0);
           elsif rectangle_3 = '1' and C_color_3 /="11"then
				  VGA_R <= color_RGB(TO_INTEGER(C_color_3))(29 downto 20);
				  VGA_G <= color_RGB(TO_INTEGER(C_color_3))(19 downto 10);
				  VGA_B <= color_RGB(TO_INTEGER(C_color_3))(9 downto 0);
           elsif rectangle_4 = '1' and C_color_4 /="011"then
				  VGA_R <= color_RGB(TO_INTEGER(C_color_4))(29 downto 20);
				  VGA_G <= color_RGB(TO_INTEGER(C_color_4))(19 downto 10);
				  VGA_B <= color_RGB(TO_INTEGER(C_color_4))(9 downto 0);
	       elsif rectangle_5 = '1' and C_color_5 /="011"then
       		      VGA_R <= color_RGB(TO_INTEGER(C_color_5))(29 downto 20);
		     	  VGA_G <= color_RGB(TO_INTEGER(C_color_5))(19 downto 10);
			      VGA_B <= color_RGB(TO_INTEGER(C_color_5))(9 downto 0);
           elsif rectangle_6 = '1' and C_color_6 /="011"then
				  VGA_R <= color_RGB(TO_INTEGER(C_color_6))(29 downto 20);
				  VGA_G <= color_RGB(TO_INTEGER(C_color_6))(19 downto 10);
				  VGA_B <= color_RGB(TO_INTEGER(C_color_6))(9 downto 0);
           elsif rectangle_7 = '1' and C_color_7 /="011"then
				  VGA_R <= color_RGB(TO_INTEGER(C_color_7))(29 downto 20);
				  VGA_G <= color_RGB(TO_INTEGER(C_color_7))(19 downto 10);
				  VGA_B <= color_RGB(TO_INTEGER(C_color_7))(9 downto 0);
           elsif rectangle_11 = '1' or  rectangle_12 = '1' or rectangle_13 = '1' or rectangle_14 = '1' or rectangle_15 = '1' or rectangle_16 = '1' then
		          VGA_R <= "1111111111";    
	    	      VGA_G <= "1111111111";
 		          VGA_B <= "0000000000"; 
           elsif vga_hblank = '0' and vga_vblank ='0' then
        		  VGA_R <= "0000000000";
       		      VGA_G <= "1111111111";
        		  VGA_B <= "0000000000";
           else
       		      VGA_R <= "0000000000";
       		      VGA_G <= "0000000000";
       		      VGA_B <= "0000000000";    
           end if;
		   end if;
    end if;
  end process VideoOut;

  VGA_CLK <= clk25;
  VGA_HS <= not vga_hsync;
  VGA_VS <= not vga_vsync;
  VGA_SYNC <= '0';
  VGA_BLANK <= not (vga_hsync or vga_vsync);

end rtl;
